MT48LC16M16A2B4-6A: G

bit. Each of the x8 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each x16 67,108,864-bit memory bank is organized into 8192 rows 512 columns of 16 bits. Read and write accesses to the SDRAM are burst-oriented; the access starts at a selected location and continues for a programmed number of locations in the programming sequence. Access begins with the registration of an active command, followed by a read or write command. The address bits registered in correspondence with the active command are used to select the bank and row to be accessed (BA[1:0] selects the bank; A[12:0] selects the row). The address bits registered in correspondence with the read or write command are used to select the starting column position of the burst access. SDRAM provides a programmable read or write burst length (BL) of 1, 2, 4, or 8 locations, or a full page, with a burst termination option. The auto-precharge function may be enabled to provide a self-timed row precharge initiated at the end of the burst sequence. The 256Mb SDRAM uses an internal pipeline architecture for high-speed operation. This architecture is compatible with the 2n rule of the prefetch architecture, but it also allows the column address to be changed every clock cycle for high-speed, completely random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycle and provide a seamless, high speed, random access operation. The 256Mb SDRAM is designed to run in 3.3V memory systems. Auto-refresh mode and power-saving and power-down modes are provided. All inputs and outputs are LVTTL compatible. Sdram provides substantial advances in DRAM operating performance, including the ability to synchronize burst data at higher data rates by automatically generating column addresses, the ability to stagger between internal banks to hide precharge time, and the ability to randomly change column addresses during bursts during each clock cycle.