CDCLVP1208RHDR

CDCLVP1208 is a highly versatile, low additive
Jitter buffer that can generate eight LVPECL copies
Clock output from one of two selectable LVPECLs
LVDS or LVCMOS input
Communication applications. It has a maximum clock
Frequency up to 2 GHz. Characteristics of CDCLVP1208
On-chip multiplexer (MUX) to select one of the two
inputs, can be easily configured only through a
control terminal. Overall additional jitter
Performance below 0.1 ps,10 kHz RMS
20 MHz with an overall output deviation as low as 20 ps
Make the device the perfect choice for use
demanding applications.
CDCLVP1208 clock buffer to allocate one of two
8 pairs of selectable clock inputs (INO,IN1)
Differential LVPECL clock output (OUT0, OUT7)
Minimum
The skew of the clock distribution.
CDCLVP1208 can accept two clock sources
Input multiplexer. Input can be LVPECL,LVDS
or LVCMOS/LVTTL.
CDCLVP1208 designed for driving.
50Ω transmission line. When driving input
Single-ended mode, LVPECL bias voltage
(VAC_REF) should be applied to unused negative numbers
Input terminals. However, for high speed performance
Up to 2 GHz, the differential mode is very powerful
Recommend.
CDCLVP1208 package in a small 28-pin
5mm x 5mm QFN Package and Features
ct-85c operation from -40 °.